In “Cascode Configuration Removes Miller Effect, Boosts PFC Performance," a cascode connection of two MOSFETs helped eliminate the Miller effect and significantly improve power factor correction (PFC) performance.
Recall that the Miller effect is a very large increase in a transistor’s apparent input capacitance due to negative feedback from the transistor’s output to input, when the transistor comprises a high-gain amplifier. A unity-gain amplifier has no Miller effect, although it may have a huge input capacitance and cause subsequent effects such as leading-edge and trailing-edge distortion associated with this input capacitance, and a charge-versus-voltage characteristic plateau.
However, the schematic that was tested and published was less than perfect for an important reason: the upper-cascode MOSFET input capacitance, Cgs, did not have a reliable discharge path. The improved design described here removes that downside and presents a viable cascode PFC schematic layout. Values and models of components used are just for demonstration and may differ depending on the purpose of the design.
The cascode PFC design is built around MOSFETs M1, M2, and M3 (Fig. 1). The previous schematic does not have M3, which serves as the M2 Cgs discharge switch. This MOSFET significantly improves the PFC characteristics, expanding the upper operating frequency if driven properly.
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| 1. This improved design adds a discharge path for the upper-cascode MOSFET’s input capacitance to improve PFC performance. |
P-channel MOSFET M3 should be controlled in-phase with the M1. An inexpensive low-voltage moderate RDS(on) transistor can be used here. Voltage source V3 represents a 12-V dc gate offset for M2, and it should be bypassed with a 10-μF ceramic capacitor. Both M1 and M3 work best if driven from a two-channel MOSFET driver such as the LTC1693-1 (Linear Technology Corp.) or similar.
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